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ESD Latch Up Behaviour in Diodes Inc. Power Switch Parts

A new customer came to me with their product that was having problems during testing at another laboratory. There were radiated emissions problems (mostly solved with improvements to the ground plane scheme on the PCB) and a very interesting (and challenging) ESD problem which I’ll cover in this blog.

Here was the device exhibiting the problem, a Diodes Inc AP22802AW5-7 “power distribution load switch”. Input VBAT from a stick of AA batteries, SW_PWR from a rotary switch, and output to the rest of the circuit.

Problem outline

The ESD problem was described by the customer:

The EUT stopped working when 4kV contact discharges were applied on discharge point shown. I removed the batteries and I put them [in] again and there was not any response from the sample (no otuput and the green LED remained OFF).

[A second sample] was then tested with the same result, although this time not on the first discharge

Upon inspection both devices had failed due to the load switch (AP22802AW5-7Diodes), with one failing open and one failing short and both becoming very warm.

ESD diode placed on input and output of load switch (with no effect)

ESD diodes placed on all [discharge points] (with no effect)

ESD diode places on VCC close to pullup resistors for [discharge points] with no effect

First thing first was to get the product set up on the ESD table (with a bit of added blur to protect the innocent).

It was very easy to re-create the problem observed at the original test lab with the second contact discharge to the EUT exposed contact point causing the unit to shut down.

In each case, the power switch was failing low resistance from IN to GND. The initial theory was that the device was being damaged by the high voltage punching through the silicon layers leaving a conductive path.

 

Eliminate the possible

I made a series of experiments to determine the coupling path into the problematic device. Working on the principle that, because of the 15cm distance between discharge point and problem device, that conduction might have been the problem.

  • Capacitors on Vin and EN
  • plus disconnect EN line
  • plus ferrite beads and capacitors on Vin, Vout and EN
  • plus local TVS diodes on pins of device
  • plus ferrite beads in series with [EUT input] lines

Whilst none of these experiments were successful they certainly helped eliminate conduction as the coupling path.

Because of the very high frequency content of the ESD pulse, capacitive coupling is likely going to be the dominant coupling method. Whilst it could couple into the device directly, there was more opportunity for the pulse to couple into the traces connected to the device first. Filtering the inputs eliminates two coupling possibilities

 

Change of sample

The PCB was starting to get a bit tired from the repeated hot air SMT de-soldering and re-soldering so I swapped to another supplied sample. To be able to operate the unit out of the casing I swapped to a linear DC bench supply instead of the AA batteries.

This proved to be an interesting mode as it allowed me to kill the power quickly. The next set of experiments were in an attempt to reduce the effect of capacitive coupling to the problem device.

  • Improved ground stitching / connection
  • Changing supply voltage
  • Indirect HCP discharge – not to EUT but to the Horizontal Coupling Plane albeit with a vertical ESD gun to increase capacitive coupling to EUT.
  • Reduction of coupling into Vin terminal by removing components and copper
  • Addition of copper foil shield over the top of the device

 

Failure mode discovery

Setting the current limit on the DC supply to a fairly low value (about 20% higher than nominal current draw) was a good idea.

When applying the ESD strikes the supply went into foldback as the EUT power input went low resistance. I discovered that quickly turning off the power and then turning it back on effectively reset the failure mode of the device. This proved to be repeatable over several discharges: zap – foldback – power cycle – EUT OK.

What silicon component behaves like this? A thyristor.

This is a phenomena known as “latch up” where the parasitic thyristor structure present in the CMOS process fires due to over voltage… such as an ESD strike for instance!

Because the device is only small the power dissipation caused by the battery short circuit current is enough to “pop” the device through overheating.

 

Out of circuit testing

Whilst it doesn’t get used very often, my Sony Tektronix 370 curve tracer is perfect for testing components like this.

(not mine, picture From CAE Online)

Here’s the VI curve of an undamaged device. It’s a bipolar voltage between VIN and GND. On the left of centre is the standard forward biased body diode. On the right is the reverse biased breakdown of around 8V.

Now for a damaged device. In this case the current changes quickly for a small applied voltage and there is no non-linear characteristic. Essentially, a short circuit.

Turning up the maximum voltage that the curve tracer can apply and dialling down the series impedance allowed me to simulate the over voltage fault condition and create a latch up condition. This latch up wasn’t permanent due to the bipolar sine wave nature of the curve tracer applied voltage.

However turning up the voltage enough to cause excess power dissipation inside the device did result in the same failure mode using the curve tracer.

 

Summary

I have never encountered a device that is this unusually sensitive to ESD events before. A nearby 2kV discharge on the PCB top layer ground plane was enough to cause the latch up condition.

I noted in the report to the customer that this device had been changed to “not recommend for new designs” by Diodes Inc. I wonder if they identified this condition in the device and withdrew it for that reason.

The customer resolved the issue by replacing the device with a different part and we all lived happily ever after.

The end.

 

 

 

When ESD Protection Gets Bypassed

ESD protection is essential to control the Electro-Static Discharge event from damaging sensitive circuitry within a product. But its location within the system needs to be considered carefully and is sometimes not obvious at the schematic level.

I’d like to share with you a great example of this that I found whilst working on a customer’s system. I probably wouldn’t have spotted this without testing but I will certainly have it in mind for future design reviews.

 

The EUT

In this instance, the Equipment Under Test is formed from a 2 part metal chassis consisting a large base and a hinged lid. On the lid there is a membrane keypad that interfaces via a Flat Flexible Cable (FFC) to the front panel PCB. There is a second ribbon cable from front panel PCB to CPU board carrying the button presses to the processor.

The ESD protection is on the front panel cable, next to the point where the unit is likely to be touched – the keys. So far, so good.

system under test showing front panel, esd protection and cables

The base and lid are connected elsewhere via the typical long piece of green and yellow wire for electrical safety purposes. The inductance of this connection (long wire, single point) means that it has minimal effect at the high frequencies present in an ESD waveform. Also, the case halves are separated by a rubber environmental seal meaning there is no contact around the edge of the case.

 

EUT + ESD = ???

So what happens when the EUT is subject to an ESD event? There is no discharge to the plastic membrane keypad on the top and discharges to the Vertical Coupling Plane don’t have any effect. However, when a discharge is made to the seam between the lid and base, something interesting happens.

Because of the conditions mentioned earlier (large seam with a significant, remote impedance connecting the lid to the base) the pulse is free to couple to the internal cable assembly as shown below.

Because the ESD protection is on the front panel display board it is unable to prevent the flow of high frequency current down the cable and into the CPU.

The effect of the discharge is to cause the entire system to reset and eventually the GPIO lines responsible for monitoring the front panel keys were damaged to the point of non functionality.

Analysis

On the face of it, the designers had acted sensibly; the ESD protection was right next to the interface that was likely to be touched by the user. However, the design of the case and the routing of the cable proved to be a problem – something that was not anticipated.

With the addition of some simple capacitive filtering or ESD protection at the point at which the cable enters the CPU board this problem was overcome.

 

Lessons

There are lessons for us all here that I would summarise as:

  1. Consider every cable as a risk, even internal ones
  2. Watch out for cables crossing enclosure seams or apertures where coupling is a risk. Not a dissimilar situation to a PCB trace crossing a split in a ground plane – and we all know how bad those can be, right?
  3. Consider how the PCBs and cables will be integrated within the system through a mechanical design review (with your EMC hat on)
  4. It doesn’t matter how well designed you think your system is, testing is necessary to find these problems